搜索资源列表
VHDL
- 高质量的VHDL代码乒乓处理FIFO缓存
FIFO
- 用VHDL语言编写的实现FIFO的设计，经编译下载成功
RS232uart(VHDL)
- 256字节深度的RS232串口程序,共分4个模块,顶层文件\\FIFO程序\\串口收和串口发.经过测试已用于产品.可靠!
fifo源程序
- fifo源程序，VHDL编写~具有一定的参考价值~-source code of a fifo, writen in VHDL, will be useful to some extent as a reference
uart8.zip
- 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。,Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to sta
trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
fifo
- FIFO 是一种先进先出数据缓存器，这是一个同步FIFO的VHDL源程序，将FIFO分成几个模块进行设计，最后用顶层文件进行模块化设计。-FIFO is a FIFO buffer, which is a synchronous FIFO in VHDL source code, will be divided into several modules FIFO design, top-level files Finally, the modular design.
mem_ctrl_latest.tar
- 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
AD7864
- 这是对上次AD7864采样程序的改进，增加了FIFO的编程，功能比上次源码更加完善！-This sourse is modified and I have added the program of FIFO,so its function is better then privious one.I hope it is helpful for you!
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
FIFOexperience
- 华为内部关于FIFO的经验之谈，深入了解FIFO-Huawei on the FIFO' s internal experiences
hdlc
- HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
FifoDesignWithVerilog
- 处理整帧数据的FIFO的巧妙控制设计,能给大家一个参考-To deal with the entire frame of data FIFO control ingenious design, give you a reference
TS_sychrous_check
- 该模块主要用于MEPGII TS流同步检测。当连续检测到3个TS包同步时，输出一个同步有效信号，在该同步信号的驱动下，TS包写入FIFO中。该模块对检测TS包的有无及是否同步特别有效，希望对做数字电视的朋友有所帮助。-The module is mainly used for synchronous detection MEPGII TS stream. When detected in three consecutive TS packets simultaneously, the outpu
usbin_v1.7
- 用于cy7c68013与fpga的从FIFO通讯.版本1.7-For the CY7C68013 and FPGA communications from the FIFO. Version 1.7
fifoi
- 基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控-Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
ps
- RS(204,188)译码器的设计 异步FIFO设计 伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计 除法器的设计 加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua
video_process_base_on_DSPandFPGA
- 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管